1. Field of the Invention
The present invention relates to semiconductor devices and fabrication methods thereof and semiconductor structures, and more particularly, to a semiconductor device and a fabrication method thereof and a semiconductor structure for improving the product yield.
2. Description of Related Art
In a conventional flip-chip package, a plurality of solder bumps are formed on bonding pads of a chip for mounting the chip on a substrate. However, as I/O counts increase and the distance between the solder bumps decreases, solder bridging easily occurs between the solder bumps. To alleviate the problem, copper pillar bumps can be formed instead of the solder bumps. But as the distance between the copper pillar bumps continuously decreases, solder bridging can still occur.
FIGS. 1A and 1B are schematic cross-sectional views showing a semiconductor device and a fabrication method thereof according to the prior art.
Referring to FIG. 1A, a substrate 10 and a chip 11 are provided. The substrate 10 has at least two adjacent connecting pads 101, and the chip 11 has at least two bonding pads 111 formed on a surface 110 thereof. Further, a passivation layer 112 is formed on the surface 110 and the bonding pads 111 and a plurality of openings 113 are formed in the passivation layer 112 for exposing the bonding pads 111. A UBM (Under Bump Metallurgy) layer 114 is formed on the bonding pads 111 exposed from the openings 113 of the passivation layer 112, and an insulating layer 115 is formed on the passivation layer 112 and around peripheries of the UBM layer 114. Then, a copper pillar 12 and a solder material 13 are sequentially formed on the UBM layer 114 on each of the bonding pads 111.
Then, referring to FIG. 1B, the copper pillars 12 are bonded to the connecting pads 101 of the substrate 10 through the solder material 13 and further encapsulated by an encapsulant 14 formed between the substrate 10 and the chip 11, thus forming a semiconductor device 1.
However, referring to FIG. 1B, since the distance D between the adjacent copper pillars 12 is quite small, solder bridging 131 easily occurs to the copper pillars 12. To overcome the drawback, the width W of the copper pillars 12 can be reduced, which however reduces the contact area between the copper pillars 12 and the UBM layer 114 and consequently increases stresses therebetween. As such, cracking easily occurs between the copper pillars 12 and the UBM layer 114. Further, since the insulating layer 115 is required in the semiconductor device 1 for reducing stresses, the fabrication cost of the semiconductor device 1 is increased.
Therefore, how to overcome the above-described drawbacks has become urgent.